-------------------------------------------------------------------------------
-- Title      : compteur programmable synchrone générique
-- Project    : 
-------------------------------------------------------------------------------
-- File       : compteur_prog_gen.vhd
-- Author     : NOUEL Patrice  <nouel@split>
-- Company    : 
-- Last update: 2004/03/23
-- Platform   : 
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2004/03/22  1.0      nouel	Created
-------------------------------------------------------------------------------



LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY compteur_prog_gen IS
  GENERIC (Nb_Bits : natural := 8; --les valeurs par defaut
           Modulo : natural := 256);  -- sont optionelles
  PORT ( h, compter, raz, charger : IN std_ulogic;
         entree : IN std_logic_vector(Nb_bits-1 DOWNTO 0);
         sortie :  OUT std_logic_vector(Nb_bits-1 DOWNTO 0));
BEGIN 
  ASSERT ----- controle des parametres
		 Modulo <= 2**Nb_bits
                           REPORT "erreur sur les parametres"
                           SEVERITY error; 
END compteur_prog_gen; 

---------------------------------------------------------------

ARCHITECTURE synchrone OF compteur_prog_gen IS 
  
SIGNAL c  : natural RANGE 0 TO Modulo -1;

BEGIN 

  P1 :PROCESS
   BEGIN  
-- description entierement synchrone 
    WAIT UNTIL RISING_EDGE(h);
    IF raz = '1' THEN
      c <=0;
    ELSIF charger = '1' THEN 
      c <= TO_integer(unsigned(entree));
    ELSIF compter = '1' THEN
      c <= (c+1) MOD Modulo;
    END IF;
  END PROCESS;
  
   sortie <= std_logic_vector(to_unsigned(c, Nb_bits));
    
END synchrone;