-- Fichier             :    cy7c150.vhd                       
-- Societe             :    ENSERB                        
-- Auteur              :    P.Nouel
-- Date de creation    :    Sep 98
-- Contenu             :    RAM CYPRESS avec e/s separees
-- Synthetisable ?     :    Non
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LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;


ENTITY cy7c150 IS
	PORT ( a : IN unsigned( 9 DOWNTO 0);
	       d : IN unsigned( 3 DOWNTO 0);
	       o : OUT unsigned( 3 DOWNTO 0);
	       rs_l, cs_l, oe_l, we_l : IN std_logic);
END cy7c150;

-- modele sans-retard d'apres catalogue CYPRESS

ARCHITECTURE sans_retard OF cy7c150 IS
	
	TYPE matrice IS ARRAY (0 TO 1023 ) OF unsigned( 3 DOWNTO 0);
	SIGNAL craz , csort, cecri : BOOLEAN;

        SIGNAL contenu : matrice;

BEGIN
	craz <= ( rs_l = '0' AND cs_l = '0');
	csort <= ( cs_l = '0' AND rs_l = '1' AND oe_l = '0' AND we_l = '1');
	cecri <= ( cs_l = '0' AND we_l = '0');

ecriture:PROCESS
	BEGIN
		WAIT ON craz, cecri;
		IF craz THEN
		    FOR i IN matrice'RANGE LOOP
			contenu(i) <= "0000";
		    END LOOP;
		ELSIF cecri THEN
		    	contenu(to_integer('0'& a)) <= d ;
		ELSE
			 o <= unsigned(contenu(to_integer('0'& a)));
		END IF;
	END PROCESS; 

-- attention , il faut rajouter '0' en bit de signe de a afin que l'entier correspondant soit positif
  			  	
END;