------------------------------------------------------------------------------- -- Title : Detection fronts -- Project : ------------------------------------------------------------------------------- -- File : fronts.vhd -- Author : -- Company : -- Last update: 2006/05/04 -- Platform : ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2006/05/04 1.0 nouel Created ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fronts IS PORT ( signal_lent : IN std_ulogic; -- front à detecter clk : IN std_ulogic; -- horloge front_montant : OUT std_ulogic; -- 1er cas front_descendant : OUT std_ulogic); -- 2eme cas END fronts; ARCHITECTURE simple OF fronts IS BEGIN -- simple Detection: PROCESS VARIABLE detect : std_logic_vector(1 DOWNTO 0); BEGIN WAIT UNTIL rising_edge (clk); -- c'est donc synchrone de clk front_montant <= '0'; front_descendant <= '0' ; detect(1) := detect(0); detect(0) := signal_lent; IF detect = "01" THEN front_montant <= '1'; END IF; IF detect = "10" THEN front_descendant <= '1'; END IF; END PROCESS; END simple;