------------------------------------------------------------------------------- -- Title : conversion hexadecimal 4 bits -7 segments -- Project : ------------------------------------------------------------------------------- -- File : hexa_to_7seg.vhd -- Author : P.Nouel -- Company : -- Last update: 2002/12/19 -- Platform : ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2002/11/30 1.0 unknown Created ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY hexa_to_7seg IS GENERIC ( anode : boolean := false ); -- choix anode ou cathode commune PORT ( hexa : IN std_logic_vector(3 DOWNTO 0); -- de 0 à F segments : OUT std_logic_vector(6 DOWNTO 0)); END hexa_to_7seg; ARCHITECTURE combinatoire OF hexa_to_7seg IS SIGNAL sortie : std_logic_vector(6 DOWNTO 0); BEGIN -- par_comptage PROCESS (hexa) BEGIN -- PROCESS CASE hexa IS WHEN "0000" => sortie <= "1111110" ; -- 0 WHEN "0001" => sortie <= "0110000" ; -- 1 WHEN "0010" => sortie <= "1101101" ; -- 2 WHEN "0011" => sortie <= "1111001" ; -- 3 WHEN "0100" => sortie <= "0110011" ; -- 4 WHEN "0101" => sortie <= "1011011" ; -- 5 WHEN "0110" => sortie <= "1011111" ; -- 6 WHEN "0111" => sortie <= "1110000" ; -- 7 WHEN "1000" => sortie <= "1111111" ; -- 8 WHEN "1001" => sortie <= "1110011" ; -- 9 WHEN "1010" => sortie <= "1110111" ; -- A WHEN "1011" => sortie <= "0011111" ; -- B WHEN "1100" => sortie <= "1001110" ; -- C WHEN "1101" => sortie <= "0111101" ; -- D WHEN "1110" => sortie <= "1001111" ; -- E WHEN OTHERS => sortie <= "1000111" ; -- F END CASE; END PROCESS; segments <= NOT sortie WHEN anode ELSE sortie; END combinatoire;