------------------------------------------------------------------------------- -- Title : latch n bits -- Project : ------------------------------------------------------------------------------- -- File : latch_gen.vhd -- Author : -- Company : ENSERB -- Last update : 2000/09/15 -- Platform : ------------------------------------------------------------------------------- -- Description : -- ------------------------------------------------------------------------------- -- Modification history : -- 1999/12/15 : created ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY latch_gen IS GENERIC ( Nb_bits : positive := 8); -- Nombre de bits PORT ( en : IN std_ulogic; entree : IN std_ulogic_vector(Nb_bits-1 DOWNTO 0); sortie : OUT std_ulogic_vector(Nb_bits-1 DOWNTO 0)); END latch_gen; ARCHITECTURE basique OF latch_gen IS BEGIN -- basique -- purpose : tant que en = '1' sortie = entree -- inputs : en, entree -- outputs : sortie p1 : PROCESS (en, entree) BEGIN -- PROCESS p1 IF en = '1' THEN sortie <= entree; END IF; END PROCESS p1; END basique ;