-- Fichier             :    ls138.vhd                       
-- Societe             :    ENSERB                        
-- Auteur              :    P.Nouel
-- Date de creation    :    1997
-- Contenu             :    decodeur binaire
-- Synthetisable ?     :    oui
------------------------------------------------------------------------
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;


ENTITY ls138 IS
	PORT (		g1, g2a, g2b, a, b, c : IN STD_ULOGIC;
		y0, y1, y2, y3, y4, y5, y6,y7 : OUT STD_ULOGIC);
END ls138;
-----------------------------------------------------------------------------

ARCHITECTURE avec_conversion OF ls138 IS

BEGIN
	PROCESS
		VARIABLE y : unsigned(0 TO 7);
		VARIABLE adresse : INTEGER RANGE 0 TO 7;
		VARIABLE AConvertir : unsigned(3 DOWNTO 0);
	BEGIN
		WAIT ON g1, g2a, g2b, a, b, c;
		AConvertir := '0' & c & b & a ;
		adresse := to_integer(AConvertir);
		y := "11111111";
		IF g1 = '1' AND g2a = '0' AND g2b = '0' THEN
			y(adresse) := '0';
		END IF;
		y0 <= y(0);
		y1 <= y(1);
		y2 <= y(2);
		y3 <= y(3);
		y4 <= y(4);
		y5 <= y(5);
		y6 <= y(6);
		y7 <= y(7);
	END PROCESS;
END;
-----------------------------------------------------------------------------
ARCHITECTURE equations OF ls138 IS

	SIGNAL valide : STD_ULOGIC;

BEGIN
	valide <= g1 AND (NOT g2a) AND (NOT g2b);
	y7 <= NOT(c AND b AND a AND valide) ;
	y6 <= NOT(c AND b AND (NOT a) AND valide);
	y5 <= NOT(c AND (NOT b) AND a AND valide);
	y4 <= NOT(c AND (NOT b) AND (NOT a) AND valide);
	y3 <= NOT((NOT c) AND b AND a AND valide);
	y2 <= NOT((NOT c) AND b AND (NOT a) AND valide);
	y1 <= NOT((NOT c) AND (NOT b) AND a AND valide);
	y0 <= NOT((NOT c) AND (NOT b) AND (NOT a) AND valide);

END equations;