-- Fichier :  multiplexeur.vhd                      
-- Societe : ENSEIRB                       
-- Auteur : P.Nouel
-- Date de creation : 9-96
----- Exemples de style d'ecriture
-- Circuit combinatoire synthetisable
------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY multiplexeur4 is
	port( entree : IN std_logic_VECTOR (3 DOWNTO 0);
		adresse : IN std_logic_VECTOR (1 DOWNTO 0);
		s : OUT std_logic);
END;
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ARCHITECTURE concurrente OF multiplexeur4 IS
BEGIN
	s <= entree(0) WHEN adresse = "00" ELSE
		entree(1) WHEN adresse = "01" ELSE
		entree(2) WHEN adresse = "10" ELSE
		entree(3) ;
END;
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ARCHITECTURE selection OF multiplexeur4 IS
BEGIN
	WITH adresse SELECT
		s  <= 	entree(0) WHEN  "00",
			entree(1) WHEN "01",
			entree(2) WHEN "10",
			entree(3) WHEN OTHERS;
END; 
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ARCHITECTURE processus_explicite OF multiplexeur4 IS
BEGIN

	PROCESS(entree, adresse)
		BEGIN
			CASE adresse IS
                          WHEN "00" => s<= entree(0);
				WHEN "01"  => s<= entree(1);
				WHEN  "10" => s <= entree(2);
				WHEN OTHERS => s <= entree(3);
			END CASE;
		END PROCESS;
END;
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LIBRARY ieee;
USE ieee.numeric_std.ALL;

ARCHITECTURE rapide OF multiplexeur4 IS
BEGIN 		
	s <= entree(to_integer(unsigned(adresse)));
END ;
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