-------------------------------------------------------------------------------
-- Titre       : multiplication par addition et decalage
-- Projet      : 
-------------------------------------------------------------------------------
-- Fichier     : multiplieur_ad1.vhd
-- Auteur      : NOUEL Patrice  <nouel@fakir>
-- Compagnie   : ENSEIRB
-- Mise a jour : 2000/12/19
-- Platform    :   
-------------------------------------------------------------------------------
-- Description : synthétisable
-- Entite se trouve dans multiplieur.vhd
-------------------------------------------------------------------------------
-- Modification history :
-- 2000/12/19 : creation
-------------------------------------------------------------------------------

--------------- SYNTHESE VHDL d'un multiplieur par additions et decalages
---
---    Initialisation : r <= 0, n1 <= a, n2 <= b
----   tantque ( n2 != 0) faire
----        si ( lsb_n2 =1) alors
--                 accumuler somme de n1      r <= n1 + r 
--          fin_si
--          decaler n1 a gauche, n2 a droite 
--     fin_tantque
--     stop
------------------------------------------------------------------------------  
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;


ARCHITECTURE mad1 OF multiplieur IS

  	TYPE type_etat IS (debut, add, dec, fin);
	SIGNAL etat : type_etat; 
	SIGNAL n1 : unsigned(2*Nbr_bits-1 DOWNTO 0);
	SIGNAL n2 : unsigned(Nbr_bits-1 DOWNTO 0);
	SIGNAL accu : unsigned(2*Nbr_bits-1 DOWNTO 0);
	SIGNAL additionner, decaler, initialiser, zero, lsb : BOOLEAN;
BEGIN
	
	
   operateurs: PROCESS
	BEGIN				 ------ sur front montant
	WAIT UNTIL rising_edge(h);
		IF initialiser THEN
			n2 <= unsigned(op2);
			n1 <=  resize(unsigned(op1),n1'length); 
			accu <= (OTHERS => '0');
		ELSIF additionner THEN
			accu <= accu + n1; 
		ELSIF decaler THEN
			n2 <= '0' & n2(Nbr_bits-1  downto 1);
			n1  <= n1(2*Nbr_bits-2 downto 0) & '0';
     		END IF; 
	END PROCESS operateurs;

	result <= std_logic_vector(accu);
	zero <= (n2 = 0);
	lsb <= (n2(0) = '1');


   sequenceur:PROCESS 
	BEGIN
	WAIT UNTIL falling_edge(h);      -- synchrone sur front montant
		IF (init = '1') THEN
			etat <= debut; 	
		ELSE   
		  CASE etat IS
			WHEN debut =>IF zero THEN etat <= fin;
				     ELSIF lsb THEN etat <= add;
				     ELSE etat <= dec;
				     END IF;		     
			WHEN add => etat <= dec;
			WHEN dec => IF zero THEN etat <= fin;
				    ELSIF lsb THEN etat <= add;
				    END IF;
			WHEN fin => etat <= fin;
    		  END CASE;
		END IF;
	END PROCESS sequenceur ;

	initialiser <= (etat = debut);
	additionner <= (etat = add);
	decaler <= (etat = dec);
        fin_calcul <= '1' WHEN etat = fin ELSE '0';
	
END mad1;