-------------------------------------------------------------------------------
-- Title      : rom 16 octets
-- Project    : 
-------------------------------------------------------------------------------
-- File       : rom16x8.vhd
-- Author     :   <nouel@AINHOA>
-- Company    : 
-- Last update: 2006/05/16
-- Platform   : 
-------------------------------------------------------------------------------
-- Description: rom synthétisable
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2006/05/15  1.0      nouel	Created
-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY rom16x8 IS
  
  PORT (
    adresse : IN  std_logic_vector(3 DOWNTO 0);
    donnees : OUT std_logic_vector(7 DOWNTO 0));

END rom16x8;


ARCHITECTURE par_table OF rom16x8 IS
  
  SIGNAL adr : natural;
  
BEGIN  -- par_table
  
  adr <= to_integer(unsigned(adresse));
  
rom: PROCESS (adr)
  BEGIN  -- PROCESS rom
    CASE adr IS
      WHEN 0 => donnees <= X"45";   -- E
      WHEN 1 => donnees <= X"4E";   -- N
      WHEN 2 => donnees <= X"53";   -- S
      WHEN 3 => donnees <= X"45";   -- E
      WHEN 4 => donnees <= X"49";   -- I
      WHEN 5 => donnees <= X"52";   -- R
      WHEN 6 => donnees <= X"42";   -- B
      WHEN 7 => donnees <= X"20";   -- 
      WHEN 8 => donnees <= X"42";   -- B
      WHEN 9 => donnees <= X"6F";   -- o
      WHEN 10 => donnees <= X"6E";  -- n
      WHEN 11 => donnees <= X"6A";  -- j
      WHEN 12 => donnees <= X"6F";  -- o
      WHEN 13 => donnees <= X"75";  -- u
      WHEN 14 => donnees <= X"72";  -- r       
      WHEN OTHERS => donnees <= X"00";             -- NUL
    END CASE;
  END PROCESS rom;
 
END par_table;