------------------------------------------------------------------------------- -- Title : test de la fonction anti rebonds -- Project : ------------------------------------------------------------------------------- -- File : test_anti_rebonds.vhd -- Author : -- Company : -- Last update: 2006/09/25 -- Platform : ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2006/09/11 1.0 nouel Created ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test_anti_rebonds IS END test_anti_rebonds; ARCHITECTURE rapide OF test_anti_rebonds IS COMPONENT anti_rebonds GENERIC ( simulation : boolean := false); PORT ( raz : IN std_ulogic; -- reset actif '1' h : IN std_ulogic; -- horloge systeme poussoir : IN std_ulogic; -- poussoir avec rebonds poussoir_propre : OUT std_ulogic); -- entree filtree END COMPONENT; SIGNAL raz,h , e, s : std_ulogic; CONSTANT periode : time := 20 ns; -- 50 MHz CONSTANT rebond : time := 35 ns ; BEGIN -- rapide A1 : anti_rebonds GENERIC MAP ( simulation => true) PORT MAP ( raz => raz, h => h, poussoir => e, poussoir_propre => s); raz <= '1', '0'AFTER 2*periode + 5 ns; PROCESS BEGIN -- PROCESS h <= '1', '0' AFTER periode/2; WAIT FOR periode; END PROCESS; -- faire un run de 14 ms e <= '0', '1' AFTER 5*periode + 2 ns, '0'AFTER 5*periode +rebond + 2 ns, '1' AFTER 5*periode + 2*rebond + 2 ns, '0' AFTER 5*periode + 8*rebond + 5 ns, '1' AFTER 5*periode + 9*rebond + 5 ns, '0' AFTER 5*periode + 10*rebond + 5 ns; END rapide;