-------------------------------------------------------------------------------
-- Title      : test des différents multiplieurs séquentiels
-- Project    : 
-------------------------------------------------------------------------------
-- File       : test_multiplieur.vhd
-- Author     : NOUEL Patrice  <nouel@split>
-- Company    : 
-- Last update: 2003/09/10
-- Platform   : 
-------------------------------------------------------------------------------
-- Description: Il faut faire un run 36.5 uS
--              Test tous les cas possibles.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/07/01  1.0      nouel	Created
-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY test_multiplieur IS  
END test_multiplieur;


ARCHITECTURE stimuli OF test_multiplieur IS 

  COMPONENT multi
    GENERIC (
    Nbr_bits : natural := 4);
  PORT	(
    SIGNAL op1  : IN std_logic_vector (Nbr_bits-1 DOWNTO 0) ;   
    SIGNAL op2  : IN std_logic_vector (Nbr_bits-1 DOWNTO 0);    
    SIGNAL init : IN std_ulogic;  
    SIGNAL  h   : IN STD_ULOGIC;      
    SIGNAL result : OUT std_logic_vector(2*Nbr_bits-1 downto 0);  
    SIGNAL fin_calcul	: OUT STD_ULOGIC); 
  END COMPONENT;

SIGNAL init, fc, h : std_ulogic;
SIGNAL e1, e2 : std_logic_vector(3 DOWNTO 0);
SIGNAL r : std_logic_vector(7 DOWNTO 0);

CONSTANT periode : time := 10 ns;       -- 100 Mhz
CONSTANT nb_bits : natural := 4;        -- on peut la changer
  
FOR m1 : multi                          -- configuration
  USE ENTITY work.multiplieur(mad2);
  
BEGIN  -- stimuli

horloge: PROCESS
BEGIN  -- PROCESS horloge
  h <= '1', '0' AFTER periode/2;
  WAIT FOR periode;
END PROCESS horloge;


M1 : multi
  GENERIC MAP (
  Nbr_bits => nb_bits)
  PORT MAP (
  op1        => e1,
  op2        => e2,
  init       => init,
  h          => h,
  result     => r,
  fin_calcul => fc);

test: PROCESS 
BEGIN  -- PROCESS stimuli
  init <= '1';
  WAIT FOR periode + periode/4;         -- un peu plus qu'une periode
  init <= '0';
   FOR i IN 0 TO 2**nb_bits-1 LOOP 
    e1 <= std_logic_vector(TO_unsigned(i,e1'length));
    FOR j IN 0 TO 2**nb_bits-1 LOOP
     e2 <= std_logic_vector(TO_unsigned(j,e2'length));
     WAIT UNTIL rising_edge(fc);           -- resultat disponible   
     ASSERT r = std_logic_vector(TO_unsigned(i*j,r'length))
                   REPORT "erreur sur le resultat" ;
      WAIT UNTIL rising_edge(h);           -- au moins une periode entre
     init <= '1', '0' AFTER periode + periode/4;  -- un peu plus qu'une periode
   END LOOP;  -- j
  END LOOP;  -- i
END PROCESS test;


END stimuli;