------------------------------------------------------------------------------- -- Title : test du registre à decalage -- Project : ------------------------------------------------------------------------------- -- File : test_reg_dec.vhd -- Author : -- Company : -- Last update: 2007/03/05 -- Platform : ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2007/03/05 1.0 nouel Created ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; ENTITY test_reg_dec IS END; ARCHITECTURE avec_table OF test_reg_dec IS COMPONENT registre GENERIC (Nb_bits : natural := 8; Tps : time := 15 ns; Tpas : time := 18 ns); PORT ( h, raz, edg, edd : IN std_ulogic; sel : IN std_ulogic_vector(1 DOWNTO 0); d_entree : IN std_ulogic_vector(Nb_bits -1 DOWNTO 0); d_sortie : OUT std_ulogic_vector(Nb_bits -1 DOWNTO 0)); END COMPONENT; --------- configuration FOR r1 : registre USE ENTITY WORK.registre_decalage(un_process); SIGNAL sel: std_ulogic_vector(1 DOWNTO 0); SIGNAL data, sortie : std_ulogic_vector(7 DOWNTO 0); SIGNAL h, raz, edg, edd : std_ulogic; TYPE entree IS RECORD sel, data : natural; -- entrees edd, edg : std_ulogic; -- entrees sortie : natural ; -- sorties END RECORD; TYPE vecteur IS ARRAY (0 TO 4) OF entree; CONSTANT valeurs : vecteur := ( ( 3, 16#AB#, '0', '0', 16#00#), --chargement ( 1, 16#01#, '0', '0', 16#AB#), -- decal d 0 ( 2, 16#02#, '0', '0', 16#55#), -- decal g 0 ( 1, 16#04#, '0', '1', 16#AA#), -- decal d 1 ( 2, 16#08#, '1', '0', 16#55#)); BEGIN -- description structurelle r1: registre GENERIC MAP ( 8, 10 ns, 20 ns) PORT MAP ( h, raz, edg, edd, sel, data, sortie); horloge : PROCESS BEGIN h <= '0', '1' AFTER 25 ns; WAIT FOR 50 ns; END PROCESS; stimuli : PROCESS BEGIN raz <= '1'; WAIT FOR 60 ns; raz <= '0'; FOR i IN vecteur'range LOOP WAIT UNTIL h'last_value = '1' AND h = '0'; sel <= std_ulogic_vector(to_unsigned(valeurs(i).sel,2)); data <= std_ulogic_vector(to_unsigned(valeurs(i).data,8)); edd <= valeurs(i).edd; edg <= valeurs(i).edg; ASSERT sortie = std_ulogic_vector(to_unsigned(valeurs(i).sortie,8)) REPORT " Tu es mauvais" ; END LOOP; ASSERT false REPORT " FIN du test"; WAIT; END PROCESS; END;