------------------------------------------------------------------------------- -- Title : test de la rom 16 x8 -- Project : ------------------------------------------------------------------------------- -- File : test_rom16x8.vhd -- Author : -- Company : -- Last update: 2006/09/26 -- Platform : ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2006/05/16 1.0 nouel Created ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY test_rom16x8 IS END test_rom16x8; ARCHITECTURE simple OF test_rom16x8 IS COMPONENT rom16x8 PORT ( adresse : IN std_logic_vector(3 DOWNTO 0); donnees : OUT std_logic_vector(7 DOWNTO 0)); END COMPONENT; SIGNAL ad : std_logic_vector(3 DOWNTO 0); SIGNAL donnees : std_logic_vector(7 DOWNTO 0); CONSTANT periode : time := 20 ns; -- 50 MHz BEGIN -- simple R1 : rom16x8 PORT MAP ( adresse => ad, donnees => donnees); -- le run total est: 16 X 20 ns = 350 ns environ parcours: PROCESS BEGIN -- PROCESS parcours FOR i IN 0 TO 15 LOOP ad <= std_logic_vector(to_unsigned(i,4)); WAIT FOR periode; END LOOP; -- i WAIT; END PROCESS parcours; END simple;