-------------------------------------------------------------------------------
-- Title      : test du modulo
-- Project    : 
-------------------------------------------------------------------------------
-- File       : test_unsigned_mod.vhd
-- Author     :   <patrice@SOLEIL>
-- Company    :  http://vhdl33.free.fr
-- Created    : 2011-03-30
-- Last update: 2011-04-06
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2011 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2011-03-30  1.0      patrice	Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY test_unsigned_mod IS  
END;

ARCHITECTURE simple OF test_unsigned_mod IS
  
  CONSTANT periode   : time := 10 ns;
  SIGNAL clk , reset, data_valid , start : std_ulogic;
  SIGNAL dividende :  std_logic_vector(23 DOWNTO 0);
  SIGNAL modulo :  std_logic_vector(7 DOWNTO 0);

  CONSTANT N1 : natural := 24;          -- Nbd bits dividende
  
BEGIN  -- simple
  
  reset <= '1', '0' AFTER periode + 3 ns;

  -- horloge
  h100 : PROCESS
  BEGIN  -- PROCESS h125
    clk <= '0', '1' AFTER periode /2;
    WAIT FOR periode;
  END PROCESS h100;

  m1 : ENTITY WORK.unsigned_modulo(un_multiplieur)
    GENERIC MAP (
      N1       => N1,
      divisor => x"C8")
    PORT MAP (
    clk        => clk,
    reset      => reset,
    start      => start,
    dividend   => dividende,
    modulo     => modulo,
    data_valid => data_valid);

  -- différents essais
  dividende <= x"005FD8" ;  -- 24536 quotient 122  modulo 136 OK
-- dividende <= x"000000" ;  --  quotient 0  modulo 0 OK
 -- dividende <= x"0000C8" ; -- quotient 1  modulo 0 OK
 --  dividende <= x"FFFFFF";   -- 16777215 quotient 83886  modulo 15 OK
 --   dividende <= x"0C7FDC";   -- 819164 quotient 4095  modulo 164 OK
 -- dividende <= x"000012";     -- 18 quotient 0 modulo 18 OK
  --   dividende <= x"FFFFFFFF";  -- 4294967295 quotient 21474836 modulo 95
                                        
  
  start <= '0', '1' AFTER 2* periode + 3 ns, '0' AFTER 4* periode ;
  -- doit rester à 1 pendant le calcul
  

END simple;