------------------------------------------------------------------------------- -- Title : test du filtres bas niveau -- Project : ------------------------------------------------------------------------------- -- File : pgmfiltre.vhd -- Author : -- Company : -- Last update : 1999/11/19 -- Platform : ------------------------------------------------------------------------------- -- Description : -- -- ------------------------------------------------------------------------------- -- Modification history : -- 1999/10/11 : created ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY PgmFiltre IS END PgmFiltre; USE work.utils.ALL; ARCHITECTURE structure OF PgmFiltre IS COMPONENT camera GENERIC ( image : string := "lena.pgm"; periode : time := 100 ns); -- frequence echantillonnage PORT ( init : OUT std_ulogic; pixel : OUT natural RANGE 0 TO 255; dispo : OUT std_ulogic; acquit : IN std_logic); END COMPONENT; COMPONENT dut PORT (h : IN std_ulogic; -- horloge init : IN std_ulogic; -- reset pixel : IN natural RANGE 0 TO 255; pix_calcul : OUT natural RANGE 0 TO 255; ready_in : IN std_ulogic; -- protocole d'entree ack_in : OUT std_ulogic; ready_out : OUT std_ulogic; ack_out : IN std_ulogic); END COMPONENT; COMPONENT moniteur GENERIC ( image : string := "lena_fil.pgm"; periode : time := 100 ns; -- frequence echantillonnage nx : natural := 512; -- points par ligne ny : natural := 512); -- nbre de lignes PORT ( init : IN std_ulogic; pixel : IN natural RANGE 0 TO 255; dispo : IN std_ulogic; acquit : OUT std_ulogic); END COMPONENT; SIGNAL h, init, ready_in, ack_in, ready_out, ack_out : std_ulogic; SIGNAL pixel, sortie : integer; -- contrainte differree FOR C1 : camera USE ENTITY work.pgm2pixel(pour_cci); FOR d1 : dut USE ENTITY work.filtre(gradient); FOR M1 : moniteur USE ENTITY work.pixel2pgm(ecriture); TYPE tableau IS ARRAY (positive RANGE <>) OF natural RANGE 0 TO 16*255; BEGIN -- par_constantes C1 : camera PORT MAP ( init => init, pixel => pixel, dispo => ready_in, acquit => ack_IN ); d1: dut PORT MAP (h, init, pixel, sortie, ready_in,ack_in,ready_out, ack_out); M1 : moniteur PORT MAP ( init => init, pixel => sortie, dispo => ready_out, acquit => ack_out); pour_circ : horloge(h, 50 ns , 50 ns); END structure;