-------------------------------------------------------------------------------
-- Title      : Design minimum
-- Project    : 
-------------------------------------------------------------------------------
-- File       : copie.vhd
-- Author     :   <patrice
-- Company    : http://vhdl33.free.fr
-- Last update: 2008/12/15
-- Platform   : 
-------------------------------------------------------------------------------
-- Description: Pour carte Altera , map des I/O par attributs VHDL
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2008/12/15  1.0      patrice Created
-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY copie IS

  PORT (
    button : IN  std_ulogic;            -- one input
    led    : OUT std_ulogic);           -- one output

END copie;


ARCHITECTURE very_simple OF copie IS

-- Syntaxe dédiée à Altera
  -- Carte de developpement stratix 2
  ATTRIBUTE chip_pin      : string;              -- Altera only
  ATTRIBUTE chip_pin OF button : SIGNAL IS "W5";     -- pin assignment
  ATTRIBUTE chip_pin OF led    : SIGNAL IS "H27";  -- pin assignment

BEGIN  -- very_simple

  led <= NOT button;

END very_simple;