-------------------------------------------------------------------------------
-- Title      : Tp PIC
-- Project    : 
-------------------------------------------------------------------------------
-- File       : pic.vhd
-- Author     :   <nouel@SARE>
-- Company    : ENSEIRB
-- Last update: 2005/01/25
-- Platform   : 
-------------------------------------------------------------------------------
-- Description: Pic embarqué sur FPGA
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/02/25  1.0      nouel	Created
-------------------------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY pic IS
  GENERIC (
    simulation : boolean := false);     -- change les constantes de temps    
  PORT (
    clk       : IN    std_logic;        -- horloge systeme
    reset_n   : IN    std_logic;        -- reset general
    int       : IN    std_logic;        -- demande interruption
    port_a    : INOUT std_logic_vector(7 DOWNTO 0);
    port_b    : INOUT std_logic_vector(7 DOWNTO 0)    );
END pic;

ARCHITECTURE structure OF pic IS
  
  COMPONENT P16F84 
    GENERIC(
      SyncReset : boolean := true);
    PORT(
      Clk : IN std_logic;
      Reset_n : IN std_logic;
      T0CKI : IN std_logic;
      INT : IN std_logic;
      Port_A : INOUT std_logic_vector(7 DOWNTO 0);
      Port_B : INOUT std_logic_vector(7 DOWNTO 0)
      );
  END COMPONENT;

  SIGNAL t0cki : std_logic;               -- entree externe timer

BEGIN  -- structure
  
  P1 : P16F84 PORT MAP (
    clk     => clk,
    reset_n => reset_n,
    T0CKI   => t0cki,
    int     => int,
    port_a  => port_a,
    port_b  => port_b);
  
  diviseur: PROCESS
    CONSTANT rapport : natural := 749;    -- si 50 Mhz alors 15 us
    CONSTANT rapport_s : natural := 9;    -- pour simu
    VARIABLE c : natural RANGE 0 TO rapport;
  BEGIN  -- PROCESS diviseur
    WAIT UNTIL rising_edge(clk);
    t0cki <= '0';
    IF simulation THEN
      IF c < rapport_s THEN             -- simulation
        c := c + 1;
      ELSE
        c := 0;
        t0cki <= '1';
      END IF;
    ELSE
      IF c < rapport THEN               -- synthèse
        c := c + 1;
      ELSE
        c := 0;
        t0cki <= '1';
      END IF;
    END IF;
  END PROCESS diviseur;
  
END structure;